As the networking of multiple types of processors, input/output units and peripherals increases in scope and complexity, many unique problems arise involving the intercommunication of commands, messages, and data between the variously interconnected modular units. It is necessary that there be taken into account means for allowing flexibility within the system, means for accommodating different types of processing units, and means for allowing partitioning, if required, all in addition to providing high system speed and throughput with proper data transfer, integrity, and error correction means. Further, networks which use only one system bus are subject to halt-down should the system bus fail so that a dual replicatable system bus can be used to eliminate this problem to provide redundancy. Such duplicatable or replicatable system busses incur some additional problems in regard to communications between the various modules.
Prior art systems such as U.S. Pat. No. 4,622,630 entitled "Data Processing System Having Unique Bus Control Protocol" involve a single common bus which is used for communication of address and data information among various system components but wherein the single bus is time multiplexed in order to provide periods for address transfer and periods for data information transfer thus slowing the throughput to some extent.
In U.S. Pat. No. 4,982,321 entitled "Dual Bus System", there is provided an architecture where two system busses are used for entirely different purposes and are not replicates of each other. Thus one bus in this system is operable for memory operations while another bus is operable for input/output operations, but there is no redundancy or means by which any one of the busses can be used for all of the necessary functions. Thus this type of system could not operate on a single bus alone since it, at all times, requires at least two busses for normal operation.
U.S. Pat. No. 4,535,448 entitled "Dual Bus Communication System" involves a dual set of busses used to provide coupling between data services and voice services of a particular AT&T communication system designated as the CS 300. In this system, one bus functions on a time division basis for communication between port circuits, while the other bus functions as a packet-switch data processing bus for interfacing system peripherals with port circuitry. Again here the busses in the system are dissimilar and are not interchangeable and thus cannot provide any redundancy.
In U.S. Pat. No. 4,933,846 entitled "Network Communications Adaptor With Dual Interleaved Memory Banks Serving Multiple Processors", the system involves dissimilar busses such that one bus functions for transferring addresses and the other functions only for the transfer of data.
The architecture of the presently disclosed system network involves particularized dual system busses which are replicates of each other but are also capable of operating independently and thus providing redundant bus transfer facilities to each of the attached digital modules. Thus each one of the two system busses involved is a duplicate of the other so that the system can operate on any one of the busses should either system bus fail.
Further the dual system busses operate on a single type of protocol which is compatible for processors having Store-Through (ST) cache memory units and also for Non-Store-Through (NST) cache memory units.
Thus the objects of the invention are to provide an enhanced throughput of data transfer operations between multiple types of processor modules, multiple memory modules, and multiple input/output interface modules and permitting, not only redundancy, but partitioning and flexibility of bus arbitration and flexibility of system operation while using a common bus protocol applicable for use of store-through and non-store through cache memories.